Chapter 9: Analog Capture Circuit
ADC_OUT
Slave: LTC1407A-1 A/D Converter
R
AD_CONV
D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13
D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13
FPGA
Master
SPI_SCK
Z
Channel 1
Z
Channel 0
Z
Converted data is presented with a latency of one sample.
The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV.
AD_CONV
SPI_SCK
Sample
point
The converted values is then presented after the next AD_CONV pulse.
Sample
point
ADC_OUT
Channel 0
13
0
Channel 1
13
0
Channel 0
13
UG334_c9_06_052407
Figure 9-6:
Analog-to-Digital Conversion Interface
Figure 9-7 shows detailed transaction timing. The AD_CONV signal is not a traditional SPI
slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC leaves
the ADC_OUT signal in the high-impedance state. As shown in Figure 9-6 , use a 34-cycle
communications sequence. The ADC 3-states its data output for two clock cycles before
and after each 14-bit data transfer.
4ns min
AD_CONV
3ns
19.6ns min
SPI_SCK
1
2
3
4
5
6
8ns
ADC_OUT
High-Z
Channel 0
13
12
11
AD_CONV
45ns min
SPI_SCK
ADC_OUT
30
Channel 1
3
2
31
1
32
0
33
6ns
34
High-Z
The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles
UG330_c10_06_032007
Figure 9-7: Detailed SPI Timing to ADC
UCF Location Constraints
Figure 9-8 provides the User Constraint File (UCF) constraints for the amplifier interface,
including the I/O pin assignment and I/O standard used.
NET "AD_CONV"
NET "SPI_SCK"
NET "AD_DOUT"
LOC = "Y6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
LOC = "AA20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
LOC = "D16" | IOSTANDARD = LVCMOS33 ;
Figure 9-8: UCF Location Constraints for the ADC Interface
76
www.xilinx.com Spartan-3A/3AN FPGA Starter Kit Board User Guide
UG334 (v1.1) June 19, 2008
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